Journals in DBLP

IEEE Trans. VLSI Syst.
1998, volume: 6, number: 3

1. V. K. Jain, S. Horiguchi
   VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:346-353 [Journal]
   
2. Christian Legl, Bernd Wurth, Klaus Eckl
   Computing support-minimal subfunctions during functional decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:354-363 [Journal]
   
3. Kang-Ngee Chia, Hea Joung Kim, S. Lansing, William H. Mangione-Smith, J. Villasensor
   High-performance automatic target recognition through data-specific VLSI. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:364-371 [Journal]
   
4. O. Kibar, Philippe J. Marchand, Sadik C. Esener
   High-speed CMOS switch designs for free-space optoelectronic MIN's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:372-386 [Journal]
   
5. Daniel Mange, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet
   Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:387-399 [Journal]
   
6. Scott Hauck, Gaetano Borriello, Carl Ebeling
   Mesh routing topologies for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:400-408 [Journal]
   
7. Karim Arabi, Bozena Kaminska, Mohamad Sawan
   On chip testing data converters using static parameters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:409-419 [Journal]
   
8. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
   Bounds on pseudoexhaustive test lengths. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:420-431 [Journal]
   
9. Irith Pomeranz, Sudhakar M. Reddy
   On methods to match a test pattern generator to a circuit-under-test. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:432-444 [Journal]
   
10. Vaughn Betz, Jonathan Rose
    Effect of the prefabricated routing track distribution on FPGA area-efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:445-456 [Journal]
    
11. Rohini Gupta, John Willis, Lawrence T. Pileggi
    Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:457-463 [Journal]
    
12. Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu
    Wave-pipelining: a tutorial and research survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:464-474 [Journal]
    
13. Bongjin Jung, Wayne P. Burleson
    Efficient VLSI for Lempel-Ziv compression in wireless data communication networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:475-483 [Journal]
    
14. Zhanping Chen, Kaushik Roy, Tan-Li Chou
    Efficient statistical approach to estimate power considering uncertain properties of primary inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:484-492 [Journal]
    
15. Marco Winzker
    Low-power arithmetic for the processing of video signals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:493-497 [Journal]
    
16. Jianmin Li, Chung-Kuan Cheng
    Routability improvement using dynamic interconnect architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:498-501 [Journal]
    
17. Franco Fummi, Donatella Sciuto, Cristina Silvano
    Automatic generation of error control codes for computer applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:502-506 [Journal]
    
18. Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto
    Testability analysis and behavioral testing of the Hopfield neural paradigm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:507-511 [Journal]