The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. VLSI Syst.
1998, volume: 6, number: 4

  1. Anantha Chandrakasan, Edwin Hsing-Mean Sha
    Special Section on Low-Power Electronics and Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:518-519 [Journal]
  2. Qing Wu, Qinru Qiu, Massoud Pedram, Chih-Shun Ding
    Cycle-accurate macro-models for RT-level power analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:520-528 [Journal]
  3. Sven Wuytack, Jean-Philippe Diguet, F. V. M. Catthoor, Hugo De Man
    Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:529-537 [Journal]
  4. P. Pant, V. K. De, A. Chatterjee
    Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:538-545 [Journal]
  5. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Low-power realization of FIR filters on programmable DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:546-553 [Journal]
  6. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    Power optimization of core-based systems by address bus encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:554-562 [Journal]
  7. Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry
    Modeling and comparing CMOS implementations of the C-element. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:563-567 [Journal]
  8. Enric Musoll, Tomás Lang, Jordi Cortadella
    Working-zone encoding for reducing the energy in microprocessor address buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:568-572 [Journal]
  9. Dinesh Somasekhar, Kaushik Roy
    LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:573-577 [Journal]
  10. Alessandro Bogliolo, Luca Benini
    Robust RTL power macromodels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:578-581 [Journal]
  11. K. Ito, Lori E. Lucke, Keshab K. Parhi
    ILP-based cost-optimal DSP synthesis with module selection and data format conversion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:582-594 [Journal]
  12. Tracy C. Denk, Keshab K. Parhi
    Synthesis of folded pipelined architectures for multirate DSP algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:595-607 [Journal]
  13. Sandeep Bhatia, Niraj K. Jha
    Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:608-619 [Journal]
  14. Jacob Savir
    Redundancy revisited. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:620-624 [Journal]
  15. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
    Interleaving buffer insertion and transistor sizing into a single optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:625-633 [Journal]
  16. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
    On circuit clustering for area/delay tradeoff under capacity and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:634-642 [Journal]
  17. Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, Julio Arceo
    The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:643-655 [Journal]
  18. N. R. Shnidman, William H. Mangione-Smith, Miodrag Potkonjak
    On-line fault detection for bus-based field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:656-666 [Journal]
  19. Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
    Efficient test-point selection for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:667-676 [Journal]
  20. Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man
    High-level address optimization and synthesis techniques for data-transfer-intensive applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:677-686 [Journal]
  21. Kiyoshi Kobayashi, Shuji Kubota, Kiyoshi Enomoto, K. Seki, K. Kawazoe, Tetsu Sakata, Y. Matsumoto, T. Hattori
    Low-power and high-quality signal transmission baseband LSIC for personal communications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:687-696 [Journal]
  22. Jongwoo Bae, Viktor K. Prasanna
    Synthesis of area-efficient and high-throughput rate data format converters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:697-706 [Journal]
  23. An-Yeu Wu, K. J. Ray Liu
    Algorithm-based low-power transform coding architectures: the multirate approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:707-718 [Journal]
  24. Nelson L. Passos, Edwin Hsing-Mean Sha
    Scheduling of uniform multidimensional systems under resource constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:719-730 [Journal]
  25. Dave Johnson, Venkatesh Akella, Bret Stott
    Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:731-740 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002