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Journals in DBLP

IEEE Trans. VLSI Syst.
1993, volume: 1, number: 1

  1. Pallab K. Chatterjee, G. B. Larrabee
    Gigabit age microelectronics and their manufacture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:7-21 [Journal]
  2. Mario Kovac, N. Ranganathan, M. Varanasi
    SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:22-30 [Journal]
  3. Raja Venkateswaran, Pinaki Mazumder
    Coprocessor design for multilayer surface-mounted PCB routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:31-45 [Journal]
  4. Fadi J. Kurdahi, Champaka Ramachandran
    Evaluating layout area tradeoffs for high level applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:46-55 [Journal]
  5. Y. He, Ugur Çilingiroglu, Edgar Sánchez-Sinencio
    A high-density and low-power charge-based Hamming network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:56-62 [Journal]
  6. Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick
    A Monte Carlo approach for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:63-71 [Journal]
  7. John A. Nestor
    Visual register-transfer description of VLSI microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:72-76 [Journal]
  8. H. Lin, Fabrizio Lombardi, M. Lu
    On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:76-79 [Journal]
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