Journals in DBLP

IEEE Trans. VLSI Syst.
1999, volume: 7, number: 1

1. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
   Power management in high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:7-15 [Journal]
   
2. Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
   Design and optimization of dual-threshold circuits for low-voltage low-power applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:16-24 [Journal]
   
3. J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, T. F. Chen
   Segmented bus design for low-power systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:25-29 [Journal]
   
4. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
   Peephole optimization of asynchronous macromodule networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:30-37 [Journal]
   
5. Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems
   The spring scheduling coprocessor: a scheduling accelerator. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:38-47 [Journal]
   
6. Tong Liu, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi
   Test generation and scheduling for layout-based detection of bridge faults in interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:48-55 [Journal]
   
7. Gauthier Lafruit, Francky Catthoor, Jan Cornelis, Hugo De Man
   An efficient VLSI architecture for 2-D wavelet image coding with novel image scan. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:56-68 [Journal]
   
8. George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar
   Multilevel hypergraph partitioning: applications in VLSI domain. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:69-79 [Journal]
   
9. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
   The memory/logic interface in FPGAs with large embedded memory arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:80-91 [Journal]
   
10. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
    COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:92-104 [Journal]
    
11. Fernando De Bernardinis, R. Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini
    An efficient VLSI architecture for real-time additive synthesis of musical signals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:105-110 [Journal]
    
12. Victor V. Zyuban, Peter M. Kogge
    Application of STD to latch-power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:111-115 [Journal]
    
13. Wang-Dauh Tseng, Kuochen Wang
    Fuzzy-based CMOS circuit partitioning in built-in current testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:116-120 [Journal]
    
14. Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds
    High performance low power array multiplier using temporal tiling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:121-124 [Journal]
    
15. Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
    Computation of lower bounds for switching activity using decision theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:125-129 [Journal]
    
16. C.-Y. Wang, K. Roy
    An activity-driven encoding scheme for power optimization in microprogrammed control unit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:130-134 [Journal]
    
17. Rong Lin, Stephan Olariu
    Efficient VLSI architectures for Columnsort. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:135-138 [Journal]
    
18. H. Mizuno, K. Ishibashi
    A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:139-144 [Journal]
    
19. F. Mu, C. Svensson
    A layout-based schematic method for very high-speed CMOS cell design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:144-148 [Journal]