Journals in DBLP

IEEE Trans. VLSI Syst.
1999, volume: 7, number: 2

1. Uwe Sparmann, H. Mueller, Sudhakar M. Reddy
   Universal delay test sets for logic networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:156-166 [Journal]
   
2. Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith
   Timing constraints for high-speed counterflow-clocked pipelining. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:167-173 [Journal]
   
3. Tom Chen, Glen Sunada, Jain Jin
   COBRA: a 100-MOPS single-chip programmable and expandable FFT. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:174-182 [Journal]
   
4. Minesh B. Amin, Bapiraju Vinnakota
   Data parallel fault simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:183-190 [Journal]
   
5. P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja
   The design of an SRAM-based field-programmable gate array. I. Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:191-197 [Journal]
   
6. Tracy C. Denk, Keshab K. Parhi
   Two-dimensional retiming [VLSI design]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:198-211 [Journal]
   
7. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
   A coding framework for low-power address and data busses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:212-221 [Journal]
   
8. Valery Sklyarov
   Hierarchical finite-state machines and their use for digital control. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:222-228 [Journal]
   
9. S. Dutta, W. Wolf
   A circuit-driven design methodology for video signal-processing datapath elements. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:229-240 [Journal]
   
10. Chung-Yu Wu, Hsin-Chin Jiang
    An improved BJT-based silicon retina with tunable image smoothing capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:241-248 [Journal]
    
11. Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan
    A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:249-257 [Journal]
    
12. Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis
    Strategy for power-efficient design of parallel systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:258-265 [Journal]
    
13. Christos A. Papachristou, Mehrdad Nourani, Mark Spining
    A multiple clocking scheme for low-power RTL design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:266-276 [Journal]
    
14. Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
    A tree-matching chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:277-280 [Journal]
    
15. Chih-Yuang Su, Shih-Am Hwang, Po-Song Chen, Cheng-Wen Wu
    An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:280-284 [Journal]