Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 11

1. Rajarshi Mukherjee, Seda Ogrenci Memik
   An Integrated Approach to Thermal Management in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1165-1174 [Journal]
   
2. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   A Scalable Synthesis Methodology for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1175-1188 [Journal]
   
3. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
   Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1189-1202 [Journal]
   
4. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
   Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1203-1215 [Journal]
   
5. Haihua Yan, Adit D. Singh
   A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1216-1226 [Journal]
   
6. Kedarnath J. Balakrishnan, Nur A. Touba
   Improving Linear Test Data Compression. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1227-1237 [Journal]
   
7. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
   Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1238-1249 [Journal]
   
8. Jun-Cheol Park, Vincent John Mooney III
   Sleepy Stack Leakage Reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1250-1263 [Journal]
   
9. Chuan Lin, Jia Wang, Hai Zhou
   Clustering for Processing Rate Optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1264-1275 [Journal]
   
10. Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
    Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1276-1281 [Journal]
    
11. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
    Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1281-1286 [Journal]
    
12. Thomas Lenart, Viktor Öwall
    Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1286-1290 [Journal]