Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 11

1. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
   An Overview of a Compiler for Mapping Software Binaries to Hardware. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1177-1190 [Journal]
   
2. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1191-1204 [Journal]
   
3. Peng Li, Zhuo Feng, Emrah Acar
   Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1205-1214 [Journal]
   
4. H. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka
   Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1215-1224 [Journal]
   
5. Jun Ma, Alexander Vardy, Zhongfeng Wang
   Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1225-1238 [Journal]
   
6. Atul Maheshwari, Wayne Burleson
   Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1239-1244 [Journal]
   
7. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
   Graphical I_DDQ Signatures Reduce Defect Level and Yield Loss. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1245-1255 [Journal]
   
8. Montek Singh, Steven M. Nowick
   The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1256-1269 [Journal]
   
9. Montek Singh, Steven M. Nowick
   The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1270-1283 [Journal]
   
10. Bao Liu, Sheldon X.-D. Tan
    Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1284-1287 [Journal]