Journals in DBLP
Dimitris Gizopoulos , Robert C. Aitken , S. Kundu Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:493-494 [Journal ] Todd J. Foster , Dennis L. Lastor , Padmaraj Singh First Silicon Functional Validation and Debug of Multicore Microprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:495-504 [Journal ] Chung-Ho Chen , Chih-Kai Wei , Tai-Hua Lu , Hsun-Wei Gao Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:505-517 [Journal ] Loganathan Lingappan , Niraj K. Jha Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:518-530 [Journal ] Yinhe Han , Yu Hu , Xiaowei Li , Huawei Li , Anshuman Chandra Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:531-540 [Journal ] Chih-Yen Lo , Chen-Hsing Wang , Kuo-Liang Cheng , Jing-Reng Huang , Chih-Wea Wang , Shin-Moe Wang , Cheng-Wen Wu STEAC: A Platform for Automatic SOC Test Integration. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:541-545 [Journal ] Divya Arora , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Architectural Support for Run-Time Validation of Program Data Properties. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:546-559 [Journal ] Mohamed Elgebaly , Manoj Sachdev Variation-Aware Adaptive Voltage Scaling System. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:560-571 [Journal ] Antonio Zenteno Ramirez , Guillermo Espinosa , Víctor H. Champac Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:572-577 [Journal ] Encarnación Castillo , Uwe Meyer-Bäse , Antonio García , Luis Parrilla , Antonio Lloris IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:578-591 [Journal ] Ja Chun Ku , Serkan Ozdemir , Gokhan Memik , Yehea I. Ismail Thermal Management of On-Chip Caches Through Power Density Minimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:592-604 [Journal ] Nachiketh R. Potlapally , Srivaths Ravi , Anand Raghunathan , Ruby B. Lee , Niraj K. Jha Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:605-609 [Journal ]