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Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 6

  1. Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown
    Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:613-623 [Journal]
  2. Tianpei Zhang, Sachin S. Sapatnekar
    Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:624-636 [Journal]
  3. J. C. Chi, H. H. Lee, S. H. Tsai, M. C. Chi
    Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:637-648 [Journal]
  4. H. Yamamoto, J. A. Davis
    Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:649-659 [Journal]
  5. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
    Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:660-671 [Journal]
  6. Scott C. Smith
    Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:672-683 [Journal]
  7. Montek Singh, Steven M. Nowick
    MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:684-698 [Journal]
  8. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:699-710 [Journal]
  9. Giorgos Dimitrakopoulos, Christos Mavrokefalidis, K. Galanopoulos, Dimitris Nikolos
    Sorter Based Permutation Units for Media-Enhanced Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:711-715 [Journal]
  10. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:716-720 [Journal]
  11. Delong Shang, Alexandre Yakovlev, Albert Koelmans, Danil Sokolov, Alexandre V. Bystrov
    Registers for Phase Difference Based Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:720-724 [Journal]
  12. Shih-Chang Hsia, Szu-Hong Wang
    Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:725-728 [Journal]
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