Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 10

1. Radu M. Secareanu, A. Marshall
   Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1065-1066 [Journal]
   
2. Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
   Utilizing Redundancy for Timing Critical Interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1067-1080 [Journal]
   
3. Vasilis F. Pavlidis, Eby G. Friedman
   3-D Topologies for Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1081-1090 [Journal]
   
4. Xin Wang, Tapani Ahonen, Jari Nurmi
   Applying CDMA Technique to Network-on-Chip. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1091-1100 [Journal]
   
5. Koichiro Noguchi, Makoto Nagata
   An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1101-1110 [Journal]
   
6. Sujan Pandey, Manfred Glesner
   Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1111-1124 [Journal]
   
7. Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas
   A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1125-1134 [Journal]
   
8. Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng
   ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1135-1143 [Journal]
   
9. Sudarshan Bahukudumbi, Krishnendu Chakrabarty
   Wafer-Level Modular Testing of Core-Based SoCs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1144-1154 [Journal]
   
10. Venkat Satagopan, Bonita Bhaskaran, W. K. Al-Assadi, S. C. Smith, S. Kakarla
    DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1155-1159 [Journal]
    
11. Chang Hong Lin, Yuan Xie, Wayne Wolf
    Code Compression for VLIW Embedded Systems Using a Self-Generating Table. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1160-1171 [Journal]
    
12. Jie Jin, Chi-Ying Tsui
    Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1172-1176 [Journal]