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Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 9

  1. N. Gupta
    A VLSI Architecture for Image Registration in Real Time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:981-989 [Journal]
  2. Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis
    Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:990-1002 [Journal]
  3. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    Run-Time Integration of Reconfigurable Video Processing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1003-1016 [Journal]
  4. Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang
    Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1017-1027 [Journal]
  5. David Kinniment, Charles E. Dike, Keith Heron, Gordon Russell, Alexandre Yakovlev
    Measuring Deep Metastability and Its Effect on Synchronizer Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1028-1039 [Journal]
  6. Seraj Ahmad, Rabi N. Mahapatra
    An Efficient Approach to On-Chip Logic Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1040-1050 [Journal]
  7. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Bryan S. Goda, John F. McDonald
    A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1051-1054 [Journal]
  8. Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima
    Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1055-1059 [Journal]
  9. Seongmoo Heo, Ronny Krashinsky, Krste Asanovic
    Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1060-1064 [Journal]
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