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Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 2

  1. A. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani
    Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:125-134 [Journal]
  2. Jonathan Rosenfeld, Eby G. Friedman
    Design Methodology for Global Resonant H-Tree Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:135-148 [Journal]
  3. Ganesh Venkataraman, Jiang Hu, Frank Liu
    Integrated Placement and Skew Optimization for Rotary Clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:149-158 [Journal]
  4. Zhijian Lu, Wei Huang, Mircea R. Stan, Kevin Skadron, John Lach
    Interconnect Lifetime Prediction for Reliability-Aware Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:159-172 [Journal]
  5. Richard F. Hobson
    A New Single-Ended SRAM Cell With Write-Assist. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:173-181 [Journal]
  6. Jason Meyer, Fatih Kocan
    Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:182-195 [Journal]
  7. Mohammad Sharifkhani, Manoj Sachdev
    Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:196-205 [Journal]
  8. Vishal Khandelwal, Ankur Srivastava
    A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:206-215 [Journal]
  9. John M. Emmert, Charles E. Stroud, Miron Abramovici
    Online Fault Tolerance for FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:216-226 [Journal]
  10. Hae-Moon Seo, YeonKug Moon, Yong-Kuk Park, Dongsu Kim, Dong-Sun Kim, Youn-Sung Lee, Kwang-Ho Won, Seong-Dong Kim, Pyung Choi
    A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:227-231 [Journal]
  11. Liang Zhang, J. M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
    Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:231-236 [Journal]
  12. Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee
    Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:236-240 [Journal]
  13. Sankalp S. Kallakuri, Alex Doboli
    Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:240-245 [Journal]
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