Journals in DBLP

IEEE Trans. VLSI Syst.
1993, volume: 1, number: 2

1. Tom Chen, Glen Sunada
   Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:88-97 [Journal]
   
2. Lishing Liu, Jih-Kwon Peir
   Cache sampling by sets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:98-105 [Journal]
   
3. Chris J. Myers, Teresa H. Y. Meng
   Synthesis of timed asynchronous circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:106-119 [Journal]
   
4. Jalil Fadavi-Ardekani
   M×N Booth encoded multiplier generator using optimized Wallace trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:120-125 [Journal]
   
5. Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, K. W. Keutzer
   Statistical timing analysis of combinational logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:126-137 [Journal]
   
6. A. Chatterjee
   Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:138-150 [Journal]
   
7. C.-S. Li, Harald S. Stone, Y. Kwark, C. M. Olsen
   Fully differential optical interconnections for high-speed digital systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:151-163 [Journal]
   
8. Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.
   Modified Booth algorithm for high radix fixed-point multiplication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:164-167 [Journal]
   
9. Smaragda Konstantinidou
   The selective extra stage butterfly. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:167-171 [Journal]
   
10. Joseph Varghese, Michael Butts, Jon Batcheller
    An efficient logic emulation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:171-174 [Journal]
    
11. A. Sharma, R. Jain
    Estimating architectural resources and performance for high-level synthesis applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:175-190 [Journal]
    
12. Keshab K. Parhi, Takao Nishitani
    VLSI architectures for discrete wavelet transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:191-202 [Journal]
    
13. Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya
    MARVLE: a VLSI chip for data compression using tree-based codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:203-214 [Journal]
    
14. T.-Y. Wuu, Sarma B. K. Vrudhula
    A design of a fast and area efficient multi-input Muller C-element. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:215-219 [Journal]
    
15. S.-Y. Kuo, S.-C. Liang
    Design and analysis of defect tolerant hierarchical sorting networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:219-223 [Journal]
    
16. C. Sul, Robert D. McLeod, Witold Pedrycz
    Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:224-228 [Journal]