Journals in DBLP

IEEE Trans. VLSI Syst.
2000, volume: 8, number: 4

1. Jian Li, R. K. Gupta
   HDL presynthesis optimizations using a tabular model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:369-378 [Journal]
   
2. Rajamohana Hegde, Naresh R. Shanbhag
   Toward achieving energy efficiency in presence of deep submicron noise. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:379-391 [Journal]
   
3. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
   ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:392-400 [Journal]
   
4. Toshiaki Miyazaki, Atsushi Takahara, Takahiro Murooka, Masaru Katayama, Takaki Ichimori, Kazuhiro Shirakawa, Akihiro Tsutsui, K. Fukami
   PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:401-414 [Journal]
   
5. Alessandro Bogliolo, Michele Favalli, Maurizio Damiani
   Enabling testability of fault-tolerant circuits by means of I_DDQ-checkable voters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:415-419 [Journal]
   
6. H. T. Nguyen, A. Chattejee
   Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:419-424 [Journal]
   
7. Gin Yee, Carl Sechen
   Clock-delayed domino for dynamic circuit design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:425-430 [Journal]
   
8. Mehrdad Nourani, Christos A. Papachristou
   Stability-based algorithms for high-level synthesis of digital ASICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:431-435 [Journal]
   
9. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
   Peak power estimation of VLSI circuits: new peak power measures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:435-439 [Journal]
   
10. O. T.-C. Chen, Wei-Lung Liu
    An FIR processor with programmable dynamic data ranges. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:440-446 [Journal]
    
11. Samuel Norman Hamilton, Alex Orailoglu
    On-line test for fault-secure fault identification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:446-452 [Journal]
    
12. Eckart Zitzler, Jürgen Teich, S. S. Bhattclcharyya
    Evolutionary algorithms for the synthesis of embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:452-455 [Journal]
    
13. J. Pihl
    Design automation with the TSPC circuit technique: a high-performance wave digital filter. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:456-460 [Journal]
    
14. Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current
    Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:460-463 [Journal]