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Journals in DBLP

IEEE Trans. VLSI Syst.
1994, volume: 2, number: 4

  1. Lars S. Nielsen, C. Niessen, Jens Sparsø, K. van Berkel
    Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:391-397 [Journal]
  2. William C. Athas, Lars J. Svensson, J. G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou
    Low-power digital systems based on adiabatic-switching principles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:398-407 [Journal]
  3. Jason Cong, Cheng-Kok Koh
    Simultaneous driver and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:408-425 [Journal]
  4. Mazhar Alidina, J. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:426-436 [Journal]
  5. Vivek Tiwari, Sharad Malik, Andrew Wolfe
    Power analysis of embedded software: a first step towards software power minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:437-445 [Journal]
  6. Farid N. Najm
    A survey of power estimation techniques in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:446-455 [Journal]
  7. Samit Chaudhuri, Robert A. Walker, J. E. Mitchell
    Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:456-471 [Journal]
  8. Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
    A C-testable carry-free divider. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:472-488 [Journal]
  9. Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz
    Fuzzy logic approach to VLSI placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:489-501 [Journal]
  10. Chaitali Chakrabarti, Li-Yu Wang
    Novel sorting network-based architectures for rank order filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:502-507 [Journal]
  11. Kaushik Roy, Sudip Nag
    Automatic synthesis of FPGA channel architecture for routability and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:508-511 [Journal]
  12. S. Kundu
    Diagnosing scan chain faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:512-516 [Journal]
  13. Charles E. Stroud
    Reliability of majority voting based VLSI fault-tolerant circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:516-521 [Journal]
  14. R. Katti
    A modified Booth algorithm for high radix fixed-point multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:522-524 [Journal]
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