Journals in DBLP

IEEE Trans. VLSI Syst.
2000, volume: 8, number: 1

1. Yanbing Li, Miriam Leeser
   HML, a novel hardware description language and its translation to VHDL. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:1-8 [Journal]
   
2. Farzan Fallah, Stan Y. Liao, Srinivas Devadas
   Solving covering problems using LPR-based lower bounds. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:9-17 [Journal]
   
3. Subodh Gupta, Farid N. Najm
   Power modeling for high-level power estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:18-29 [Journal]
   
4. Mohammed A. S. Khalid, Jonathan Rose
   A novel and efficient routing architecture for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:30-39 [Journal]
   
5. Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
   Cut-based functional debugging for programmable systems-on-chip. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:40-51 [Journal]
   
6. Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang
   An adaptive fuzzy logic controller: its VLSI architecture and applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:52-60 [Journal]
   
7. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
   Estimation for maximum instantaneous current through supply lines for CMOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:61-73 [Journal]
   
8. Song Chen, A. Postula
   Synthesis of custom interleaved memory systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:74-83 [Journal]
   
9. Alexander Marquardt, Vaughn Betz, Jonathan Rose
   Speed and area tradeoffs in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:84-93 [Journal]
   
10. Uming Ko, Poras T. Balsara
    High-performance energy-efficient D-flip-flop circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:94-98 [Journal]
    
11. Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto
    Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:98-103 [Journal]
    
12. Wei-Chang Tsai, C. B. Shung, Sheng-Jyh Wang
    Two systolic architectures for modular multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:103-107 [Journal]