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Journals in DBLP

IEEE Trans. VLSI Syst.
1994, volume: 2, number: 1

  1. Daniel Audet, Yvon Savaria, N. Arel
    Pipelining communications in large VLSI/ULSI systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:1-10 [Journal]
  2. Catherine H. Gebotys
    An optimization approach to the synthesis of multichip architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:11-20 [Journal]
  3. Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King
    MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:21-32 [Journal]
  4. Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, J. C. Curlander
    VLSI systolic binary tree-searched vector quantizer for image compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:33-44 [Journal]
  5. Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel
    Block-oriented programmable design with switching network interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:45-53 [Journal]
  6. J. Ghosh, A. Varma, N. Krishnamurthy
    Distributed control schemes for fast arbitration in large crossbar networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:54-67 [Journal]
  7. Steve C.-Y. Huang, Wayne Wolf
    Performance-driven synthesis in controller-datapath systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:68-80 [Journal]
  8. Lih-Gwo Jeng, Liang-Gee Chen
    Rate-optimal DSP synthesis by pipeline and minimum unfolding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:81-88 [Journal]
  9. Sungho Kang, Stephen A. Szygenda
    The simulation automation system (SAS); concepts, implementation, and results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:89-99 [Journal]
  10. Brian S. Cherkauer, Eby G. Friedman
    Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:100-114 [Journal]
  11. Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson
    The yield enhancement of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:115-123 [Journal]
  12. Vojin G. Oklobdzija
    An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:124-128 [Journal]
  13. Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang
    A Gaussian synapse circuit for analog VLSI neural networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:129-133 [Journal]
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