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Journals in DBLP

IEEE Trans. VLSI Syst.
1994, volume: 2, number: 3

  1. Chien-In Henry Chen, Joel T. Yuen
    Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:273-291 [Journal]
  2. Hong-Shin Jun, Sun-Young Hwang
    Design of a pipelined datapath synthesis system for digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:292-303 [Journal]
  3. Alex Orailoglu, Ramesh Karri
    Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:304-311 [Journal]
  4. Ming-Bo Lin, A. Yavuz Oruç
    A fault-tolerant permutation network modulo arithmetic processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:312-319 [Journal]
  5. Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
    Logic design error diagnosis and correction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:320-332 [Journal]
  6. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified timing verification and the transition delay of a logic circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:333-342 [Journal]
  7. P. G. Tzionas, P. G. Tsalides, A. Thanailakis
    A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:343-353 [Journal]
  8. R. V. Pelletier, Robert D. McLeod
    Loop based design for wafer scale systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:354-357 [Journal]
  9. Chang N. Zhang, J. H. Weston, Y.-F. Yan
    Determining objective functions in systolic array designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:357-360 [Journal]
  10. K. Tsang, Belle W. Y. Wei
    A VLSI architecture for a real-time code book generator and encoder of a vector quantizer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:360-364 [Journal]
  11. Barry S. Fagin, C. Renard
    Field programmable gate arrays and floating point arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:365-367 [Journal]
  12. Jacob Savir, Srinivas Patil
    On broad-side delay test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:368-372 [Journal]
  13. A. Yakovlev, A. Petrov, L. Lavagno
    A low latency asynchronous arbitration circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:372-377 [Journal]
  14. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    Power-delay characteristics of CMOS adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:377-381 [Journal]
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