Journals in DBLP

IEEE Trans. VLSI Syst.
1997, volume: 5, number: 1

1. S. K. Tewksbury, Glenn H. Chapman
   Guest Editorial Foreword to the Special Section on WSI'95. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:1-2 [Journal]
   
2. Zahava Koren, Israel Koren
   On the effect of floorplanning on the yield of large area integrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:3-14 [Journal]
   
3. Vijay K. Jain, Lei Lin
   Complex-argument universal nonlinear cell for rapid prototyping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:15-27 [Journal]
   
4. Yves Audet, Glenn H. Chapman
   Yield improvement of a large area magnetic field sensor array using redundancy schemes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:28-33 [Journal]
   
5. Shantanu Dutt, Fran Hanchek
   REMOD: a new methodology for designing fault-tolerant arithmetic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:34-56 [Journal]
   
6. Ahmed Amine Jerraya, Gert Goossens
   Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:57-58 [Journal]
   
7. Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
   Synthesis of pipelined DSP accelerators with dynamic scheduling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:59-68 [Journal]
   
8. Samit Chaudhuri, S. A. Blthye, Robert A. Walker
   A solution methodology for exact design space exploration in a three-dimensional design space. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:69-81 [Journal]
   
9. Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan
   Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:82-100 [Journal]
   
10. Herman Schmit, Donald E. Thomas
    Synthesis of application-specific memory designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:101-111 [Journal]
    
11. Rainer Leupers, Peter Marwedel
    Time-constrained code compaction for DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:112-122 [Journal]
    
12. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and minimization techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:123-135 [Journal]
    
13. Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya
    Protocol selection and interface generation for HW-SW codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:136-144 [Journal]
    
14. Luigi Raffo, Silvio P. Sabatini, M. Mantelli, A. De Gloria, Giacomo M. Bisio
    Design of an ASIP architecture for low-level visual elaborations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:145-153 [Journal]