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Journals in DBLP

IEEE Trans. VLSI Syst.
1995, volume: 3, number: 1

  1. Mani B. Srivastava, Miodrag Potkonjak
    Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:2-19 [Journal]
  2. Mani B. Srivastava, Robert W. Brodersen
    System level hardware module generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:20-35 [Journal]
  3. Debabrata Ghosh, S. K. Nandy
    Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:36-48 [Journal]
  4. Mircea R. Stan, Wayne P. Burleson
    Bus-invert coding for low-power I/O. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:49-58 [Journal]
  5. Michael Nicolaidis, Vladimir Castro Alves, H. Bederr
    Testing complex couplings in multiport memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:59-71 [Journal]
  6. Krishnendu Chakrabarty, John P. Hayes
    Cumulative balance testing of logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:72-83 [Journal]
  7. Jun-Dong Cho, M. Sarrafzadeh
    A buffer distribution algorithm for high-performance clock net optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:84-98 [Journal]
  8. Brian S. Cherkauer, Eby G. Friedman
    A unified design methodology for CMOS tapered buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:99-111 [Journal]
  9. Steven G. Duvall
    A practical methodology for the statistical design of complex logic products for performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:112-123 [Journal]
  10. Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee
    Physical models and algorithms for optoelectronic MCM layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:124-135 [Journal]
  11. M. Agarwala, Poras T. Balsara
    An architecture for a DSP field-programmable gate array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:136-141 [Journal]
  12. Nan-Chi Chou, Chung-Kuan Cheng
    On general zero-skew clock net construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:141-146 [Journal]
  13. Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
    C-testable design techniques for iterative logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:146-152 [Journal]
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