Journals in DBLP

IEEE Trans. VLSI Syst.
1996, volume: 4, number: 2

1. Pradip K. Jha, Nikil D. Dutt
   High-level library mapping for arithmetic components. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:157-169 [Journal]
   
2. Raj S. Mitra, Partha S. Roop, Anupam Basu
   A new algorithm for implementation of design functions by available devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:170-180 [Journal]
   
3. Smita Bakshi, Daniel D. Gajski
   Component selection for high-performance pipelines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:181-194 [Journal]
   
4. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
   A real-time clustering microchip neural engine. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:195-209 [Journal]
   
5. Qing Zhu, Wayne Wei-Ming Dai
   Planar clock routing for high performance chip and package co-design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:210-226 [Journal]
   
6. Uwe Sparmann, Sudhakar M. Reddy
   On the effectiveness of residue code checking for parallel two's complement multipliers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:227-239 [Journal]
   
7. Charles J. Alpert, Andrew B. Kahng
   A general framework for vertex orderings with applications to circuit clustering. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:240-246 [Journal]
   
8. Stephen B. Furber, P. Day
   Four-phase micropipeline latch control circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:247-253 [Journal]
   
9. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
   Synthesis of initializable asynchronous circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:254-263 [Journal]
   
10. Stanislaw J. Piestrak
    Design of minimal-level PLA self-testing checkers for m-out-of-n codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:264-272 [Journal]
    
11. Samit Chaudhuri, Robert A. Walker
    Computing lower bounds on functional units before scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:273-279 [Journal]
    
12. Hong Shin Jun, Sun Young Hwang
    Automatic synthesis of dynamically configured pipelines supporting variable data initiation intervals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:279-285 [Journal]
    
13. José Luis Neves, Eby G. Friedman
    Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:286-291 [Journal]
    
14. KiJong Lee, Kiyoung Choi
    Self-timed divider based on RSD number system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:292-295 [Journal]
    
15. Mahesh A. Iyer, Miron Abramovici
    FIRE: a fault-independent combinational redundancy identification algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:295-301 [Journal]