The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. VLSI Syst.
1996, volume: 4, number: 4

  1. A. Grzeszczak, Mrinal K. Mandal, Sethuraman Panchanathan
    VLSI implementation of discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:421-433 [Journal]
  2. Srilata Raman, Lalit M. Patnaik
    Performance-driven MCM partitioning through an adaptive genetic algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:434-444 [Journal]
  3. R. Ramachandran, Shih-Lien Lu
    Efficient arithmetic using self-timing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:445-454 [Journal]
  4. Sang-Soo Lee, C. A. Laber
    A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:455-463 [Journal]
  5. Nader Mir-Fakhraei
    ATM switching architectures for wafer-scale integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:464-471 [Journal]
  6. Mark B. Josephs, Jelio T. Yantchev
    CMOS design of the tree arbiter element. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:472-476 [Journal]
  7. Qingjian Yu, Ernest S. Kuh, Tianxiong Xue
    Moment models of general transmission lines with application to interconnect analysis and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:477-494 [Journal]
  8. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002