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Journals in DBLP

IEEE Trans. VLSI Syst.
1997, volume: 5, number: 4

  1. Jun Ma, Han-Bin Liang, R. A. Pryor, Sunny Cheng, M. H. Kaneshiro, C. S. Kyono, Ken Papworth
    Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:352-359 [Journal]
  2. M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf
    The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:360-368 [Journal]
  3. Xinghai Tang, Vivek De, James D. Meindl
    Intrinsic MOSFET parameter fluctuations due to random dopant placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:369-376 [Journal]
  4. Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
    A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:377-387 [Journal]
  5. Ram K. Krishnamurthy, L. Richard Carley
    Exploring the design space of mixed swing quadrail for low-power digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:388-400 [Journal]
  6. Godi Fisher, James C. Daly, Conrad W. Recksiek, Kevin D. Friedland
    A programmable temperature monitoring device for tagging small fish: a prototype chip development. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:401-407 [Journal]
  7. Qiuting Huang, Philipp Basedau
    Design considerations for high-frequency crystal oscillators digitally trimmable to sub-ppm accuracy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:408-416 [Journal]
  8. Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki
    Instruction buffering to reduce power in processors for signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:417-424 [Journal]
  9. Vadim Gutnik, Anantha P. Chandrakasan
    Embedded power supply for low-power DSP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:425-435 [Journal]
  10. Jui-Ming Chang, Massoud Pedram
    Energy minimization using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:436-443 [Journal]
  11. Mircea R. Stan, Wayne P. Burleson
    Low-power encodings for global communication in CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:444-455 [Journal]
  12. A. Tuagi
    Entropic bounds on FSM switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:456-464 [Journal]
  13. Olivier Coudert
    Gate sizing for constrained delay/power/area optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:465-472 [Journal]
  14. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò
    Gate-level power and current simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:473-488 [Journal]
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