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Journals in DBLP

IEEE Trans. VLSI Syst.
1997, volume: 5, number: 2

  1. Mohamed Nekili, Guy Bois, Yvon Savaria
    Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:161-174 [Journal]
  2. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Scheduling tests for VLSI systems under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:175-185 [Journal]
  3. Yen-Tai Lai, Ping-Tsung Wang
    Hierarchical interconnection structures for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:186-196 [Journal]
  4. Steve C.-Y. Huang, Wayne Wolf
    Unifiable scheduling and allocation for minimizing system cycle time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:197-210 [Journal]
  5. Yongjin Jeong, Wayne P. Burleson
    VLSI array algorithms and architectures for RSA modular multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:211-217 [Journal]
  6. W. H. Wolf
    An architectural co-synthesis algorithm for distributed, embedded computing systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:218-229 [Journal]
  7. D. Zhang, Mohamed I. Elmasry
    VLSI compressor design with applications to digital neural networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:230-233 [Journal]
  8. Pi-Yu Chung, Ibrahim N. Hajj
    Diagnosis and correction of multiple logic design errors in digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:233-237 [Journal]
  9. C.-K. V. Tien, K. Lewis, Hans J. Greub, T. Tsen, John F. McDonald
    Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:238-243 [Journal]
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