Journals in DBLP

IEEE Trans. VLSI Syst.
1999, volume: 7, number: 3

1. C. Chakrabarti, C. Mumford
   Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:289-298 [Journal]
   
2. B. Bosi, Guy Bois, Yvon Savaria
   Reconfigurable pipelined 2-D convolvers for fast digital signal processing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:299-308 [Journal]
   
3. Preeti Ranjan Panda, Nikil D. Dutt
   Low-power memory mapping through reducing address bus activity. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:309-320 [Journal]
   
4. P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja
   The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:321-330 [Journal]
   
5. Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
   A design space exploration scheme for data-path synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:331-338 [Journal]
   
6. M. Inamori, Jiro Naganuma, M. Endo
   A memory-based architecture for MPEG2 system protocol LSIs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:339-344 [Journal]
   
7. Yuan-Hau Yeh, Chen-Yi Lee
   Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:345-358 [Journal]
   
8. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
   Information-theoretic bounds on average signal transition activity [VLSI systems]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:359-368 [Journal]
   
9. Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni
   VLSI architectures for turbo codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:369-379 [Journal]
   
10. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A structure-oriented power modeling technique for macrocells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:380-391 [Journal]
    
11. Michele Favalli, Cecilia Metra
    Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:392-396 [Journal]