Journals in DBLP

IEEE Trans. VLSI Syst.
1998, volume: 6, number: 1

1. Pinaki Mazumder
   Guest Editorial Special Section On Impacts Of Emerging Technologies On VLSI Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:4-5 [Journal]
   
2. Andreas Thiede, Zhi-Gong Wang, Michael Schlechtweg, M. Lang, P. Leber, Zhihao Lao, U. Nowotny, V. Hurm, M. Rieger-Motzer, M. Ludwig, M. Sedler, K. Kohler, W. Bronner, J. Hornung, A. Hulsmann, G. Kaufel, B. Raynor, J. Schneider, T. Jakobus, J. Schroth, Manfred Berroth
   Mixed signal integrated circuits based on GaAs HEMTs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:6-17 [Journal]
   
3. Roberto Sarmiento, V. de Armas, José Francisco López, Juan A. Montiel-Nelson, Antonio Núñez
   A CORDIC processor for FFT computation and its implementation using gallium arsenide technology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:18-30 [Journal]
   
4. Terry J. Fountain, Michael J. B. Duff, D. G. Crawley, C. D. Tomlinson, C. D. Moffat
   The use of nanoelectronic devices in highly parallel computing systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:31-38 [Journal]
   
5. H. Okazaki, T. Nakagawa, M. Muraguchi, H. Fukuyama, K. Maezawa, Masafumi Yamamoto
   Sampling phase detector using a resonant tunneling high electron mobility transistor for microwave phase-locked oscillators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:39-42 [Journal]
   
6. M. Fujii, K. Numata, T. Maeda, M. Tokushima, S. Wada, M. Fukaishi, M. Ishikawa
   A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:43-46 [Journal]
   
7. Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge
   Overview of complementary GaAs technology for high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:47-51 [Journal]
   
8. Pete M. Campbell, Hans J. Greub, Atul Garg, A. Steidl, Steven R. Carlough, Matthew W. Ernest, Robert F. Philhower, Cliff A. Maier, Russell P. Kraft, John F. McDonald
   A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:52-55 [Journal]
   
9. Luis A. Plana, Steven M. Nowick
   Architectural optimization for low-power nonpipelined asynchronous systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:56-65 [Journal]
   
10. Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
    Statistical estimation of average power dissipation using nonparametric techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:65-73 [Journal]
    
11. N. Maheshwari, S. Sapatnekar
    Efficient retiming of large circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:74-83 [Journal]
    
12. Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
    SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:84-100 [Journal]
    
13. S. K. Jain, Leilei Song, Keshab K. Parhi
    Efficient semisystolic architectures for finite-field arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:101-113 [Journal]
    
14. M. Aberbour, A. Houelle, Habib Mehrez, N. Vaucher, Alain Guyot
    On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:114-121 [Journal]
    
15. Bapiraju Vinnakota, Jason Andrews
    Fast fault translation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:122-133 [Journal]
    
16. Chuan-Yu Wang, Kaushik Roy
    Maximum power estimation for CMOS circuits using deterministic and statistical approaches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:134-140 [Journal]
    
17. Stuart F. Oberman, Michael J. Flynn
    Minimizing the complexity of SRT tables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:141-149 [Journal]
    
18. L. K. John, E. John
    A dynamically reconfigurable interconnect for array processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:150-157 [Journal]
    
19. Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
    Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:158-167 [Journal]
    
20. Arvind Srinivasan, G. D. Huber, David P. LaPotin
    Accurate area and delay estimation from RTL descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:168-172 [Journal]
    
21. Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata
    A novel design of a two operand normalization circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:173-176 [Journal]
    
22. Paul G. Ryan, W. Kent Fuchs
    Dynamic fault dictionaries and two-stage fault isolation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:176-180 [Journal]