Journals in DBLP

IEEE Trans. VLSI Syst.
1998, volume: 6, number: 2

1. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
   The Transmogrifier-2: a 1 million gate rapid-prototyping system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:188-198 [Journal]
   
2. Akihiro Tsutsui, Toshiaki Miyazaki
   ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunication data processing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:199-211 [Journal]
   
3. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
   Low overhead fault-tolerant FPGA systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:212-221 [Journal]
   
4. R. Glenn Wood, Rob A. Rutenbar
   FPGA routing and routability estimation via Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:222-231 [Journal]
   
5. Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses
   Some experiments about wave pipelining on FPGA's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:232-237 [Journal]
   
6. Brian Von Herzen
   Signal processing at 250 MHz using high-performance FPGA's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:238-246 [Journal]
   
7. Michael J. Wirthlin, Brad L. Hutchings
   Improving functional density using run-time circuit reconfiguration [FPGAs]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:247-256 [Journal]
   
8. M. Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim
   Fault-tolerant self-organizing map implemented by wafer-scale integration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:257-265 [Journal]
   
9. William Fornaciari, P. Gubian, Donatella Sciuto, Cristina Silvano
   Power estimation of embedded systems: a hardware/software codesign approach. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:266-275 [Journal]
   
10. Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi
    Testing configurable LUT-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:276-283 [Journal]
    
11. Klaus Herrmann, Jan Otterstedt, H. Jeschke, M. Kuboschek
    A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm² monolithic implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:284-291 [Journal]
    
12. Luca Breveglieri, Luigi Dadda
    A VLSI inner product macrocell. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:292-298 [Journal]
    
13. Uming Ko, Poras T. Balsara, Ashwini K. Nanda
    Energy optimization of multilevel cache architectures for RISC and CISC processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:299-308 [Journal]
    
14. Krishnendu Chakrabarty, John P. Hayes
    Zero-aliasing space compaction of test responses using multiple parity signatures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:309-313 [Journal]
    
15. Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio
    Time multiplexed color image processing based on a CNN with cell-state outputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:314-322 [Journal]
    
16. S. Bose, P. Agrawal, V. D. Agrawal
    A rated-clock test method for path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:323-331 [Journal]
    
17. S. Bose, P. Agrawal
    Concurrent fault simulation on message passing multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:332-342 [Journal]