Journals in DBLP

IEEE Trans. VLSI Syst.
2000, volume: 8, number: 5

1. Allen C.-H. Wu, Nikil D. Dutt
   Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:469-471 [Journal]
   
2. Petru Eles, Alex Doboli, Paul Pop, Zebo Peng
   Scheduling with bus access optimization for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:472-491 [Journal]
   
3. Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha
   Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:492-502 [Journal]
   
4. Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
   Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:503-516 [Journal]
   
5. Ying Zhao, Sharad Malik
   Exact memory size estimation for array computations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:517-521 [Journal]
   
6. Wonyong Sung, Soonhoi Ha
   Memory efficient software synthesis with mixed coding style from dataflow graphs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:522-526 [Journal]
   
7. Dominique Borrione, Julia Dushina, Laurence V. Pierre
   A compositional model for the functional verification of high-level synthesis results. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:526-530 [Journal]
   
8. Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain
   Expression-tree-based algorithms for code compression on embedded RISC architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:530-533 [Journal]
   
9. Bassam Shaer, Sami A. Al-Arian, David L. Landis
   Partitioning sequential circuits for pseudoexhaustive testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:534-541 [Journal]
   
10. Montek Singh, Steven M. Nowick
    Synthesis for logical initializability of synchronous finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:542-557 [Journal]
    
11. Christian Pacha, U. Auer, C. Burwick, Peter Glösekötter, A. Brennemann, W. Prost, F.-J. Tegude, K. F. Goser
    Threshold logic circuit design of parallel adders using resonant tunneling devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:558-572 [Journal]
    
12. Allen E. Sjogren, Chris J. Myers
    Interfacing synchronous and asynchronous modules within a high-speed pipeline. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:573-583 [Journal]
    
13. Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram
    Improving the efficiency of Monte Carlo power estimation [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:584-593 [Journal]
    
14. Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi
    A new approach to built-in self-testable datapath synthesis based on integer linear programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:594-605 [Journal]
    
15. F. Caignet, S. D.-B. Dhia, E. Sicard
    On the measurement of crosstalk in integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:606-609 [Journal]
    
16. Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik
    Line coverage of path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:610-614 [Journal]
    
17. Pasquale Corsonello, Stefania Perri, G. Cororullo
    Area-time-power tradeoff in cellular arrays VLSI implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:614-624 [Journal]
    
18. Antonio G. M. Strollo, E. Napoli, C. Cimino
    Analysis of power dissipation in double edge-triggered flip-flops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:624-629 [Journal]
    
19. Chingwei Yeh, Yin-Shuin Kang
    Cell-based layout techniques supporting gate-level voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:629-633 [Journal]
    
20. Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
    Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:633-636 [Journal]