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Journals in DBLP

IEEE Trans. VLSI Syst.
2000, volume: 8, number: 6

  1. P. Christie, Dirk Stroobandt
    The interpretation and application of Rent's rule. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:639-648 [Journal]
  2. Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:649-659 [Journal]
  3. Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl
    Heterogeneous architecture models for interconnect-motivated system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:660-670 [Journal]
  4. Arifur Rahman, Rafael Reif
    System-level performance evaluation of three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:671-678 [Journal]
  5. P. Christie
    Rent exponent prediction methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:679-688 [Journal]
  6. Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
    A compact physical via blockage model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:689-692 [Journal]
  7. Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
    Using dynamic cache management techniques to reduce energy in general purpose processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:693-708 [Journal]
  8. Gayles Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The design of the MGAP-2: a micro-grained massively parallel array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:709-716 [Journal]
  9. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
    Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:717-723 [Journal]
  10. S. Chattopadhyay, S. Adhikari, S. Sengupta, M. Pal
    Highly regular, modular, and cascadable design of cellular automata-based pattern classifier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:724-735 [Journal]
  11. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Improving path delay testability of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:736-741 [Journal]
  12. D. L. Hung, H. D. Cheng, S. Sengkhamyong
    Design of a configurable accelerator for moment computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:741-746 [Journal]
  13. Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
    GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:747-750 [Journal]
  14. Bassam Shaer, David L. Landis, Sami A. Al-Arian
    Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:750-754 [Journal]
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