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Journals in DBLP
- Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois
Design of self-checking fully differential circuits and boards. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:113-128 [Journal]
- Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:129-137 [Journal]
- Scott Hauck, Matthew M. Hosler, Thomas W. Fry
High-performance carry chains for FPGA's. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:138-147 [Journal]
- Janardhan H. Satyanarayana, Keshab K. Parhi
Theoretical analysis of word-level switching activity in the presence of glitching and correlation. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:148-159 [Journal]
- Leilei Song, Keshab K. Parhi, I. Kuroda, T. Nishitani
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:160-172 [Journal]
- Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
MetaCore: an application-specific programmable DSP development system. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:173-183 [Journal]
- Johnny Öberg, A. Kumar, Ahmed Hemani
Grammar-based hardware synthesis from port-size independent specifications. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:184-194 [Journal]
- Yehea I. Ismail, Eby G. Friedman
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:195-206 [Journal]
- Frederik Vermeulen, Francky Catthoor, Diederik Verkest, Hugo De Man
Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:207-216 [Journal]
- David Kinniment, Alexandre Yakovlev, B. Gao
Synchronous and asynchronous A-D conversion. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:217-220 [Journal]
- Ronald D. Blanton, John P. Hayes
On the design of fast, easily testable ALU's. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:220-223 [Journal]
- Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:223-228 [Journal]
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