Journals in DBLP

IEEE Trans. VLSI Syst.
2001, volume: 9, number: 6

1. Asim Smailagic
   Guest editorial: system level design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:741-742 [Journal]
   
2. Luc Séméria, Koichi Sato, Giovanni De Micheli
   Synthesis of hardware models in C with pointers and complex data structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:743-756 [Journal]
   
3. Manish Bhardwaj, Rex Min, Anantha P. Chandrakasan
   Quantifying and enhancing power awareness of VLSI systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:757-772 [Journal]
   
4. F. Wolf, R. Ernst, Wei Ye
   Path clustering in software timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:773-782 [Journal]
   
5. J. Smith, G. De Micheli
   Polynomial circuit models for component matching in high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:783-800 [Journal]
   
6. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye
   Influence of compiler optimizations on system power. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:801-804 [Journal]
   
7. Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas
   Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:805-812 [Journal]
   
8. Rajamohana Hegde, Naresh R. Shanbhag
   Soft digital signal processing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:813-823 [Journal]
   
9. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
   TAO: regular expression-based register-transfer level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:824-832 [Journal]
   
10. Xiaobo Sharon Hu, Tao Zhou, Edwin Hsing-Mean Sha
    Estimating probabilistic timing performance for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:833-844 [Journal]
    
11. Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
    Automatic generation and compaction of March tests for memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:845-857 [Journal]
    
12. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A framework for reconfigurable computing: task scheduling and context management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:858-873 [Journal]
    
13. Huapeng Wu, M. Anwar Hasan
    Efficient exponentiation using weakly dual basis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:874-879 [Journal]
    
14. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino
    Parameterized RTL power models for soft macros. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:880-887 [Journal]
    
15. D. Harris, S. Naffziger
    Statistical clock skew modeling with data delay variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:888-898 [Journal]
    
16. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:899-912 [Journal]
    
17. P. Christie
    A differential equation for placement analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:913-921 [Journal]
    
18. James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Impact of three-dimensional architectures on interconnects in gigascale integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:922-928 [Journal]
    
19. Jason Cong, Tianming Kong, Z. D. Pan
    Buffer block planning for interconnect planning and prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:929-937 [Journal]
    
20. Peter Verplaetse, Dirk Stroobandt, Jan M. Van Campenhout
    A stochastic model for the interconnection topology of digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:938-942 [Journal]
    
21. S. Bodapati, F. N. Najm
    Prelayout estimation of individual wire lengths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:943-958 [Journal]
    
22. Javier D. Bruguera, Tomás Lang
    Multilevel reverse most-significant carry computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:959-962 [Journal]
    
23. Yehea I. Ismail, Eby G. Friedman, J. L. Neves
    Exploiting the on-chip inductance in high-speed clock distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:963-973 [Journal]
    
24. Marcello Lajolo
    Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:974-982 [Journal]
    
25. Chingwei Yeh, Yin-Shuin Kang
    Cell-based layout techniques supporting gate-level voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:983-986 [Journal]