Journals in DBLP

IEEE Trans. VLSI Syst.
2001, volume: 9, number: 5

1. King-Chu Hung, Yao-Shan Hung, Yu-Jung Huang
   A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:565-576 [Journal]
   
2. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
   Technology mapping for high-performance static CMOS and pass transistor logic designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:577-589 [Journal]
   
3. Muhammad M. Khellah, Mohamed I. Elmasry
   A low-power high-performance current-mode multiport SRAM. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:590-598 [Journal]
   
4. Elie Torbey, John P. Knight
   Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:599-607 [Journal]
   
5. Massimo Alioto, Gaetano Palumbo
   Power estimation in adiabatic circuits: a simple and accurate model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:608-615 [Journal]
   
6. Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
   On gate level power optimization using dual-supply voltages. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:616-629 [Journal]
   
7. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
   Discrete-time battery models for system-level low-power design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:630-640 [Journal]
   
8. Dilip V. Sarwate, Naresh R. Shanbhag
   High-speed architectures for Reed-Solomon decoders. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:641-655 [Journal]
   
9. Youngsoo Shin, Kiyoung Choi, Young-hoon Chang
   Narrow bus encoding for low-power DSP systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:656-660 [Journal]
   
10. Hyungwon Kim, John P. Hayes
    Delay fault testing of IP-based designs via symbolic path modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:661-678 [Journal]
    
11. Irith Pomeranz, Sudhakar M. Reddy
    Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:679-689 [Journal]
    
12. Per Bjuréus, Axel Jantsch
    Modeling of mixed control and dataflow systems in MASCOT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:690-703 [Journal]
    
13. Xiaohong Jiang, Susumu Horiguchi
    Statistical skew modeling for general clock distribution networks in presence of process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:704-717 [Journal]
    
14. Zhanping Chen, Liqiong Wei, Kaushik Roy
    On effective I_DDQ testing of low-voltage CMOS circuits using leakage control techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:718-725 [Journal]
    
15. Chang-Ki Kwon, Kwyro Lee
    Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:726-729 [Journal]
    
16. Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang
    An on-chip march pattern generator for testing embedded memory cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:730-735 [Journal]