Journals in DBLP

IEEE Trans. VLSI Syst.
2001, volume: 9, number: 2

1. Michael Gschwind, Valentina Salapura, D. Maurer
   FPGA prototyping of a RISC processor core for embedded applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:241-250 [Journal]
   
2. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
   Unified functional decomposition via encoding for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:251-260 [Journal]
   
3. Rong Lin
   Reconfigurable parallel inner product processor architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:261-272 [Journal]
   
4. J. Henkel, R. Ernst
   An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:273-289 [Journal]
   
5. Irith Pomeranz, Sudhakar M. Reddy
   A built-in self-test method for diagnosis of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:290-296 [Journal]
   
6. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
   A hardware cost minimized fast Phong shader. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:297-304 [Journal]
   
7. Curt Schurgers, Francky Catthoor, Marc Engels
   Memory optimization of MAP turbo decoder algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:305-312 [Journal]
   
8. S. Dutta
   Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:313-328 [Journal]
   
9. Yi-Min Jiang, Kwang-Ting Cheng
   Vector generation for power supply noise estimation and verification of deep submicron designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:329-340 [Journal]
   
10. Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh
    Fast floorplanning for effective prediction and construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:341-351 [Journal]
    
11. Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta
    A physical design tool for built-in self-repairable RAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:352-364 [Journal]
    
12. M. Olivieri
    Design of synchronous and asynchronous variable-latency pipelined multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:365-376 [Journal]
    
13. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of application-specific systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:377-383 [Journal]
    
14. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:383-389 [Journal]
    
15. P. Pant, R. K. Roy, A. Chattejee
    Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:390-394 [Journal]
    
16. Mircea R. Stan
    Low-power CMOS with subvolt supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:394-400 [Journal]
    
17. Joseph N. Kozhaya, Farid N. Najm
    Power estimation for large sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:400-407 [Journal]
    
18. Abdel Ejnioui, N. Ranganathan
    A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:407-410 [Journal]