Journals in DBLP

IEEE Trans. VLSI Syst.
2002, volume: 10, number: 6

1. Yehea I. Ismail, Byron Krauter
   Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:683-684 [Journal]
   
2. Yehea I. Ismail
   On-chip inductance cons and pros. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:685-694 [Journal]
   
3. Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, B. J. Rubin, H. H. Smith
   A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:695-711 [Journal]
   
4. Michael W. Beattie, Lawrence T. Pileggi
   On-chip induction modeling: basics and advanced methods. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:712-729 [Journal]
   
5. Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi
   Inductance model and analysis methodology for high-speed on-chip interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:730-745 [Journal]
   
6. Haitian Hu, Sachin S. Sapatnekar
   Efficient inductance extraction using circuit-aware techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:746-761 [Journal]
   
7. Andrey V. Mezhiba, Eby G. Friedman
   Inductive properties of high-performance power distribution grids. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:762-776 [Journal]
   
8. C. Svensson
   Electrical interconnects revitalized. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:777-788 [Journal]
   
9. Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White
   Managing on-chip inductive effects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:789-798 [Journal]
   
10. Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
    Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:799-805 [Journal]
    
11. Massimo Alioto, Gaetano Palumbo
    Analysis and comparison on full adder block in submicron technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:806-823 [Journal]
    
12. Stelian Alupoaei, Srinivas Katkoori
    Net-based force-directed macrocell placement for wirelength optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:824-835 [Journal]
    
13. Chunhong Chen, Jiang Zhao, M. Ahmadi
    Probability-based approach to rectilinear Steiner tree problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:836-843 [Journal]
    
14. D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    A clock power model to evaluate impact of architectural and technology optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:844-855 [Journal]
    
15. Tony Givargis, Frank Vahid, Jörg Henkel
    Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:856-863 [Journal]
    
16. Ramesh Karri, Kaijie Wu
    Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:864-875 [Journal]
    
17. Kamal S. Khouri, Niraj K. Jha
    Leakage power analysis and reduction during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:876-885 [Journal]
    
18. Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
    Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:886-901 [Journal]
    
19. Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi
    Area-efficient high-speed decoding schemes for turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:902-912 [Journal]
    
20. Wai Chung, T. Lo, M. Sachdev
    A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:913-918 [Journal]
    
21. Farzan Fallah, Pranav Ashar, Srinivas Devadas
    Functional vector generation for sequential HDL models under an observability-based code coverage metric. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:919-923 [Journal]
    
22. Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen
    Design of a dynamic pipelined architecture for fuzzy color correction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:924-929 [Journal]
    
23. Rung-Bin Lin, Chi-Ming Tsai
    Theoretical analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:929-934 [Journal]
    
24. P. Oehler, Christoph Grimm, Klaus Waldschmidt
    A methodology for system-level synthesis of mixed-signal applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:935-942 [Journal]
    
25. Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
    ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:942-949 [Journal]