The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. VLSI Syst.
2002, volume: 10, number: 3

  1. Karam S. Chatha, Ranga Vemuri
    Hardware-software partitioning and pipelined scheduling of transformative applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:193-208 [Journal]
  2. Katherine Compton, Zhiyuan Li, James Cooley, Stephen Knol, Scott Hauck
    Configuration relocation and defragmentation for run-time reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:209-220 [Journal]
  3. Yonghee Im, Kaushik Roy
    O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:221-229 [Journal]
  4. Anoop Iyer, Diana Marculescu
    Microarchitecture-level power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:230-239 [Journal]
  5. Byoung-Woon Kim, Chong-Min Kyung
    Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:240-252 [Journal]
  6. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Cosimulation-based power estimation for system-on-chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:253-266 [Journal]
  7. Jin-Fu Li, Cheng-Wen Wu
    Efficient FFT network testing and diagnosis schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:267-278 [Journal]
  8. Guido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni
    Architectural strategies for low-power VLSI turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:279-285 [Journal]
  9. Yehia Massoud, Jacob K. White
    Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:286-291 [Journal]
  10. Khurram Muhammad, Kaushik Roy
    Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:292-300 [Journal]
  11. João Navarro Jr., Wilhelmus A. M. Van Noije
    Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:301-308 [Journal]
  12. Jatuchai Pangjun, Sachin S. Sapatnekar
    Low-power clock distribution using multiple voltages and reduced swings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:309-318 [Journal]
  13. Mondira Deb Pant, Pankaj Pant, D. Scott Wills
    On-chip decoupling capacitor optimization using architectural level prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:319-326 [Journal]
  14. Rolando Ramírez Ortiz, John P. Knight
    Compatible cell connections for multifamily dynamic logic gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:327-340 [Journal]
  15. Paul-Peter Sotiriadis, Anantha P. Chandrakasan
    A bus energy model for deep submicron technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:341-350 [Journal]
  16. Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
    Vertically integrated SOI circuits for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:351-362 [Journal]
  17. Jianwen Zhu, Daniel D. Gajski
    An ultra-fast instruction set simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:363-373 [Journal]
  18. Fatih Kocan, Daniel G. Saab
    Correction to "ATPG for combinational circuits on configurable hardware". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:374-374 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002