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Journals in DBLP

IEEE Trans. VLSI Syst.
2002, volume: 10, number: 4

  1. Fadi J. Kurdahi
    Guest editorial special issue on system synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:377-378 [Journal]
  2. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich
    SPI - a system model for heterogeneously specified embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:379-389 [Journal]
  3. Catherine H. Gebotys
    A network flow approach to memory bandwidth utilization in embedded DSP core processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:390-398 [Journal]
  4. Juanjo Noguera, Rosa M. Badia
    HW/SW codesign techniques for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:399-415 [Journal]
  5. Tony Givargis, Frank Vahid, Jörg Henkel
    System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:416-422 [Journal]
  6. Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
    Efficient hardware controller synthesis for synchronous dataflow graph in system level design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:423-428 [Journal]
  7. Forrest Brewer, Steve Haynal
    Symbolic NFA scheduling of a RISC microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:429-434 [Journal]
  8. Oscal T.-C. Chen, R. R.-B. Sheen, S. Wang
    A low-power adder operating on effective dynamic data ranges. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:435-453 [Journal]
  9. Jörg Henkel, Yanbing Li
    Avalanche: an environment for design space exploration and optimization of low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:454-468 [Journal]
  10. Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
    Skewed CMOS: noise-tolerant high-performance low-power static circuit family. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:469-476 [Journal]
  11. L.-D. Van
    A new 2-D systolic digital filter architecture without global broadcast. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:477-486 [Journal]
  12. Kevin T. Tang, Eby G. Friedman
    Simultaneous switching noise in on-chip CMOS power distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:487-493 [Journal]
  13. Zhong-Fang Jin, J.-J. Laurin, Yvon Savaria
    A practical approach to model long MIS interconnects in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:494-507 [Journal]
  14. Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
    A technique for Improving dual-output domino logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:508-511 [Journal]
  15. Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, K. J. Lee
    An efficient BIST method for distributed small buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:512-515 [Journal]
  16. Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man
    A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:515-518 [Journal]
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