Journals in DBLP

IEEE Trans. VLSI Syst.
2002, volume: 10, number: 5

1. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
   Minimizing memory access energy in embedded systems by selective instruction compression. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:521-531 [Journal]
   
2. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
   Noise constrained transistor sizing and power optimization for dual Vs_t domino logic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:532-541 [Journal]
   
3. Gang Qu, Miodrag Potkonjak
   Techniques for energy-efficient communication pipeline design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:542-549 [Journal]
   
4. Philip Heng Wai Leong, Isvan K. H. Leung
   A microcoded elliptic curve processor using FPGA technology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:550-559 [Journal]
   
5. José C. Monteiro, Arlindo L. Oliveira
   Implicit FSM decomposition applied to low-power design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:560-565 [Journal]
   
6. Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
   Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:566-581 [Journal]
   
7. A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl
   Electrical and optical clock distribution networks for gigascale microprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:582-594 [Journal]
   
8. M. Olivieri
   Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:595-600 [Journal]
   
9. Massoud Pedram, Qing Wu
   Battery-powered digital CMOS design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:601-607 [Journal]
   
10. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    VLSI circuits for low-power high-speed asynchronous addition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:608-613 [Journal]
    
11. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power data forwarding for VLIW embedded architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:614-622 [Journal]
    
12. R. Tessier, S. Jana
    Incremental compilation for parallel logic verification systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:623-636 [Journal]
    
13. Liming Xiu, Zhihong You
    A "flying-adder" architecture of frequency and phase synthesis with scalability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:637-649 [Journal]
    
14. Chantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Bengt Svantesson, Ahmed Hemani, F. Wolf
    Dynamic memory management methodology applied to embedded telecom network systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:650-667 [Journal]
    
15. Nur A. Touba
    Circular BIST with state skipping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:668-672 [Journal]
    
16. Dohyung Kim, Chan-Eun Rhee, Soonhoi Ha
    Combined data-driven and event-driven scheduling technique for fast distributed cosimulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:672-678 [Journal]