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Journals in DBLP

IEEE Trans. VLSI Syst.
2002, volume: 10, number: 1

  1. Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
    Leakage control with efficient use of transistor stacks in single threshold CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:1-5 [Journal]
  2. A. Manzak, C. Chakrabarti
    A low power scheduling scheme with resources operating at multiple voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:6-14 [Journal]
  3. You-Sung Chang, Chong-Min Kyung
    Conforming block inversion for low power memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:15-19 [Journal]
  4. Ahmed M. Shams, T. K. Darwish, Magdy A. Bayoumi
    Performance analysis of low-power 1-bit CMOS full adder cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:20-29 [Journal]
  5. Mehrdad Nourani, Christos A. Papachristou
    False path exclusion in delay analysis of RTL structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:30-43 [Journal]
  6. Ing-Jer Huang, Ping-Huei Xie
    Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:44-54 [Journal]
  7. Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
    Least-square estimation of average power in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:55-58 [Journal]
  8. G. N. Hoyer, Gin Yee, Carl Sechen
    Locally clocked pipelines and dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:58-62 [Journal]
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