Journals in DBLP

IEEE Trans. VLSI Syst.
2003, volume: 11, number: 5

1. Vivek De, Luca Benini
   Guest editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:753-754 [Journal]
   
2. Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai
   VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:755-761 [Journal]
   
3. Joong-Seok Moon, William C. Athas, Sigfrid D. Soli, Jeffrey T. Draper, Peter A. Beerel
   Voltage-pulse driven harmonic resonant rail drivers for low-power applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:762-777 [Journal]
   
4. Victor V. Zyuban
   Optimization of scannable latches for low energy. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:778-788 [Journal]
   
5. Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter M. Kogge
   Energy-efficient issue queue design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:789-800 [Journal]
   
6. Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog
   Micro-operation cache: a power aware frontend for variable instruction length ISA. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:801-811 [Journal]
   
7. Johan A. Pouwelse, Koen Langendoen, Henk J. Sips
   Application-directed voltage scaling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:812-826 [Journal]
   
8. Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt
   Adaptive low-power address encoding techniques using self-organizing lists. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:827-834 [Journal]
   
9. M. A. I. Mostafa, Sherif H. K. Embabi, Mostafa Elmala
   A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:835-838 [Journal]
   
10. Mandeep Singh, Israel Koren
    Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:839-852 [Journal]
    
11. Sungbae Hwang, Jacob A. Abraham
    Test data compression and test time reduction using an embedded microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:853-862 [Journal]
    
12. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:863-870 [Journal]
    
13. M. Maymandi-Nejad, Manoj Sachdev
    A digitally programmable delay element: design and analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:871-878 [Journal]
    
14. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
    Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:879-887 [Journal]
    
15. T. Chen, S. Naffziger
    Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:888-899 [Journal]
    
16. Yehea I. Ismail
    Improved model-order reduction by using spacial information in moments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:900-908 [Journal]
    
17. Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills
    Modeling technology impact on cluster microprocessor performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:909-920 [Journal]
    
18. Ashok K. Murugavel, N. Ranganathan
    Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:921-927 [Journal]
    
19. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    Memory allocation and mapping in high-level synthesis - an integrated approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:928-938 [Journal]
    
20. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    A high-speed energy-efficient 64-bit reconfigurable binary adder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:939-943 [Journal]
    
21. Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf
    A dictionary-based en/decoding scheme for low-power data buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:943-951 [Journal]
    
22. Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
    Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:951-954 [Journal]
    
23. Sandeep Koranne
    Design of reconfigurable access wrappers for embedded core based SoC test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:955-960 [Journal]