Journals in DBLP

IEEE Trans. VLSI Syst.
2003, volume: 11, number: 1

1. Phillip Christie
   Guest editorial: System-level interconnect prediction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:1-2 [Journal]
   
2. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
   Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal]
   
3. Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie
   Multi-objective optimization of interconnect geometry. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:15-23 [Journal]
   
4. J. Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout
   A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:24-34 [Journal]
   
5. Dirk Stroobandt
   A priori wire length distribution models with multiterminal nets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:35-43 [Journal]
   
6. Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif
   Wiring requirement and three-dimensional integration technology for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:44-54 [Journal]
   
7. Phillip Christie, José Pineda de Gyvez
   Prelayout interconnect yield prediction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:55-59 [Journal]
   
8. M. Hutton, K. Adibsamii, A. Leaver
   Adaptive delay estimation for partitioning-driven PLD placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:60-63 [Journal]
   
9. Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
   Energy-efficient skewed static logic with dual Vt: design and synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:64-70 [Journal]
   
10. Abdel Ejnioui, N. Ranganathan
    Multiterminal net routing for partial crossbar-based multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:71-78 [Journal]
    
11. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware interconnect power optimization in domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:79-89 [Journal]
    
12. M. P. Leong, P. H. W. Leong
    A variable-radix digit-serial design methodology and its application to the discrete cosine transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:90-104 [Journal]
    
13. Arindam Mukherjee, Malgorzata Marek-Sadowska
    Wave steering to integrate logic and physical syntheses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:105-120 [Journal]
    
14. Michael Nicolaidis
    Carry checking/parity prediction adders and ALUs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:121-128 [Journal]
    
15. Ken S. Stevens, Ran Ginosar, Shai Rotem
    Relative timing [asynchronous design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:129-140 [Journal]
    
16. T. J. Thorp, G. S. Yee, C. M. Sechen
    Design and synthesis of dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:141-149 [Journal]
    
17. Kyung-Saeng Kim, Kwyro Lee
    Low-power and area-efficient FIR filter implementation suitable for multiple taps. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:150-153 [Journal]