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Journals in DBLP

IEEE Trans. VLSI Syst.
2003, volume: 11, number: 6

  1. Xun Liu, Marios C. Papaefthymiou
    Design of a 20-mb/s 256-state Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:965-975 [Journal]
  2. Mohammad M. Mansour, Naresh R. Shanbhag
    High-throughput LDPC decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:976-996 [Journal]
  3. Woo-Suk Ko, Joon-Seok Kim, Young-Cheol Park, Tai-Ho Koh, Dae Hee Youn
    An efficient DMT modem for the G.LITE ADSL transceiver. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:997-1005 [Journal]
  4. Joohee Kim, Marios C. Papaefthymiou
    Block-based multiperiod dynamic memory design for low data-retention power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1006-1018 [Journal]
  5. Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach
    A model for battery lifetime analysis for organizing applications on a pocket computer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1019-1030 [Journal]
  6. Ashok K. Murugavel, N. Ranganathan
    A game theoretic approach for power optimization during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1031-1043 [Journal]
  7. Amit Sinha, Nathan Ickes, Anantha P. Chandrakasan
    Instruction level and operating system profiling for energy exposed software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1044-1057 [Journal]
  8. C. H.-I. Kim, Hendrawan Soeleman, Kaushik Roy
    Ultra-low-power DLMS adaptive filter for hearing aid applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1058-1067 [Journal]
  9. Qinwei Xu, Pinaki Mazumder
    Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1068-1079 [Journal]
  10. Volkan Kursun, Eby G. Friedman
    Domino logic with variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1080-1093 [Journal]
  11. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1094-1105 [Journal]
  12. Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi
    PD/SOI SRAM performance in presence of gate-to-body tunneling current. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1106-1113 [Journal]
  13. T. Felicijan, Stephen B. Furber
    An asynchronous ternary logic signaling system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1114-1119 [Journal]
  14. Saurabh N. Adya, Igor L. Markov
    Fixed-outline floorplanning: enabling hierarchical design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1120-1135 [Journal]
  15. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Scheduling battery usage in mobile systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1136-1143 [Journal]
  16. M. A. Azadpour, T. S. Kalkur
    A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1143-1146 [Journal]
  17. Li Ding 0002, Pinaki Mazumder
    Simultaneous switching noise analysis using application specific device modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1146-1152 [Journal]
  18. O. Milter, Avinoam Kolodny
    Crosstalk noise reduction in synthesized digital logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1153-1158 [Journal]
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