Journals in DBLP
Eero Aho , Jarno Vanne , Timo D. Hämäläinen , Kimmo Kuusilinna Configurable implementation of parallel memory based real-time video downscaler. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:283-292 [Journal ] Soontae Kim , Narayanan Vijaykrishnan , Mary Jane Irwin Reducing non-deterministic loads in low-power caches via early cache set resolution. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:293-301 [Journal ] Darrin M. Hanna , Michael DuChene Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:302-312 [Journal ] Andrej Zemva , Matjaz Verderber FPGA-oriented HW/SW implementation of the MPEG-4 video decoder. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:313-325 [Journal ] Devaraj Ayavoo , Michael J. Pont , Michael Short , Stephen Parker Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:326-334 [Journal ] A. Jameel , M. Y. Siyal , N. Ahmed Transform-domain and DSP based secure speech communication system. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:335-346 [Journal ] Nikolaos Kavvadias , Vasiliki Giannakopoulou , Spiridon Nikolaidis Development of a customized processor architecture for accelerating genetic algorithms. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:347-359 [Journal ] L. E. M. Brackenbury , W. Shao Lowering power in an experimental RISC processor. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:5, pp:360-368 [Journal ]