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Journals in DBLP

Microprocessors and Microsystems
2007, volume: 31, number: 5

  1. Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna
    Configurable implementation of parallel memory based real-time video downscaler. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:283-292 [Journal]
  2. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reducing non-deterministic loads in low-power caches via early cache set resolution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:293-301 [Journal]
  3. Darrin M. Hanna, Michael DuChene
    Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:302-312 [Journal]
  4. Andrej Zemva, Matjaz Verderber
    FPGA-oriented HW/SW implementation of the MPEG-4 video decoder. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:313-325 [Journal]
  5. Devaraj Ayavoo, Michael J. Pont, Michael Short, Stephen Parker
    Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:326-334 [Journal]
  6. A. Jameel, M. Y. Siyal, N. Ahmed
    Transform-domain and DSP based secure speech communication system. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:335-346 [Journal]
  7. Nikolaos Kavvadias, Vasiliki Giannakopoulou, Spiridon Nikolaidis
    Development of a customized processor architecture for accelerating genetic algorithms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:347-359 [Journal]
  8. L. E. M. Brackenbury, W. Shao
    Lowering power in an experimental RISC processor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:360-368 [Journal]
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