Journals in DBLP

J. Low Power Electronics
2006, volume: 2, number: 1

1. Johan Vounckx, Vassilis Paliouras
   Editorial. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:- [Journal]
   
2. Wei-Shen Wang, Michael Liu, Michael Orshansky
   Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:1-7 [Journal]
   
3. Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor
   Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:9-1 [Journal]
   
4. Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
   Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:18-26 [Journal]
   
5. Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
   A Load-Store Queue Design Based on Predictive State Filtering. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:27-36 [Journal]
   
6. Pankaj Golani, Peter A. Beerel
   Back-Annotation in High-Speed Asynchronous Design. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:37-44 [Journal]
   
7. David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin
   On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:45-55 [Journal]
   
8. Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici
   Analysis and Optimization of MPSoC Reliability. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:56-69 [Journal]
   
9. Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini
   Energy-Efficient Value Based Selective Refresh for Embedded DRAMS. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:70-79 [Journal]
   
10. Josep Rius, Maurice Meijer, José Pineda de Gyvez
    An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:80-86 [Journal]
    
11. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, J. Viejo
    Accurate Logic-Level Current Estimation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:87-94 [Journal]
    
12. Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, Jean-Didier Legat
    Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:95-104 [Journal]
    
13. Cristiano Forzan, Davide Pandini, Mariagrazia Graziano
    Power Supply Selective Mapping for Accurate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:105-112 [Journal]
    
14. Radu Zlatanovici, Borivoje Nikolic
    Power - Performance Optimization for Custom Digital Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:113-120 [Journal]
    
15. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Transistor Sizing of Logic Gates to Maximize Input Delay Variability. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:121-128 [Journal]