Journals in DBLP

J. Low Power Electronics
2006, volume: 2, number: 2

1. Daniele Paolo Scarpazza, Carlo Brandolese
   A Fast, Dynamic, Fine-Detail, Source Level Technique to Estimate the Energy Consumed by Embedded Software on Single-Issue Processor Cores. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:129-139 [Journal]
   
2. Bramha Allu, Wei Zhang 0002
   Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:140-147 [Journal]
   
3. Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones
   A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:148-164 [Journal]
   
4. Dongkun Shin, Jihong Kim
   Communication Power Optimization for Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:165-176 [Journal]
   
5. Yangdong Deng, Peng Li
   Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:177-188 [Journal]
   
6. Ali Mahdoum, Nadjib Badache, Hamid Bessalah
   An Efficient Assignment of Voltages and Optional Cycles for Maximizing Rewards in Real-Time Systems with Energy Constraints. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:189-200 [Journal]
   
7. Jia Di, Jiann S. Yuan
   Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:201-216 [Journal]
   
8. Sarvesh H. Kulkarni, Dennis Sylvester
   Power Distribution Techniques for Dual VDD Circuits. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:217-229 [Journal]
   
9. Feng Gao, John P. Hayes
   Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:230-239 [Journal]
   
10. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
    Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:240-250 [Journal]
    
11. Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark
    Subthreshold to Above Threshold Level Shifter Design. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:251-258 [Journal]
    
12. Srikanth Mohan, Arun Ravindran, David Binkley, Arindam Mukherjee
    Power Optimized Design of CMOS Programmable Gain Amplifiers. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:259-270 [Journal]
    
13. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Reducing Power Dissipation in SRAM during Test. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:271-280 [Journal]
    
14. Chris J. Bleakley, Miguel Casas-Sanchez, Jose Rizo-Morente
    Software Level Power Consumption Models and Power Saving Techniques for Embedded DSP Processors. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:281-290 [Journal]
    
15. Raimon Casanova, Ángel Dieguez, Anna Arbat, Josep Samitier
    Multiclock Domain and Dynamic Frequency Scaling Applied to the Control Unit of a Battery Powered for 1 cm3 Microrobot. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:291-299 [Journal]
    
16. Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:300-307 [Journal]
    
17. G. Evans, João Goes, Nuno F. Paulino
    Low-Voltage Low-Power Broadband CMOS Analogue Circuit for White Gaussian Noise Generation. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:308-316 [Journal]
    
18. Juan Antonio Gómez Galán, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio J. López-Martín, C. Rubia-Marcos
    Super Class AB OTAs Based on Low-Power Adaptive Techniques at the Input Stage and the Active Load. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:317-324 [Journal]