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Journals in DBLP

J. Low Power Electronics
2006, volume: 2, number: 3

  1. Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
    Energy Estimation of the Memory Subsystem in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:325-332 [Journal]
  2. Kaveh Aasaraai, Amirali Baniasadi
    Low-Power Perceptron Branch Predictor. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:333-341 [Journal]
  3. Linwei Niu, Gang Quan
    System Wide Dynamic Power Management for Weakly Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:342-355 [Journal]
  4. Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris
    Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:356-364 [Journal]
  5. Soheil Ghiasi
    An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:365-377 [Journal]
  6. Yuanlin Lu, Vishwani D. Agrawal
    CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:378-387 [Journal]
  7. Mahadevan Gomathisankaran, Akhilesh Tyagi
    WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:388-400 [Journal]
  8. Huifang Qin, Rakesh Vattikonda, Thuan Trinh, Yu Cao, Jan M. Rabaey
    SRAM Cell Optimization for Ultra-Low Power Standby. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:401-411 [Journal]
  9. Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark
    Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:412-424 [Journal]
  10. K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
    Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:425-436 [Journal]
  11. H. Pooya Forghani-zadeh, Gabriel A. Rincón-Mora
    Low-Power CMOS Ramp Generator Circuit for DC-DC Converters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:437-441 [Journal]
  12. Mohamed Ghorbel, Ahmed Ben Hamida, Mounir Samet, Jean Thomas
    An Advanced Low Power and Versatile CMOS Current Driver for Multi-Electrode Cochlear Implant Microstimulator. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:442-455 [Journal]
  13. Z. Abid, Hayssam El-Razouk
    Defect Tolerant Voter Designs Based on Transistor Redundancy. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:456-463 [Journal]
  14. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:464-476 [Journal]
  15. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Scan-Based Structure with Reduced Static and Dynamic Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:477-487 [Journal]
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