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Journals in DBLP

J. Low Power Electronics
2007, volume: 3, number: 1

  1. Wei-Shen Wang, Michael Orshansky
    Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:1-12 [Journal]
  2. Yongkui Han, Israel Koren, C. Mani Krishna
    TILTS: A Fast Architectural-Level Transient Thermal Simulation Method. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:13-21 [Journal]
  3. Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun
    Heuristic on a Novel Power Management System Cooperating with Compiler. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:22-27 [Journal]
  4. Anand Ramalingam, Anirudh Devgan, David Z. Pan
    Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:28-35 [Journal]
  5. Giuseppe Notarangelo, Francesco Pappalardo 0002, Elena Salurso, Elio Guidetti
    A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:36-42 [Journal]
  6. Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai
    Exploiting Speculation Cost Prediction in Power-Aware Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:43-53 [Journal]
  7. Joachim Fenkes, Tobias Gemmeke, Jens Leenstra
    Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:54-59 [Journal]
  8. Steven D. Tucker, Arun Ravindran, Christopher Wichman, Arindam Mukherjee
    Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:60-69 [Journal]
  9. David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
    Improving the Performance of Static CMOS Gates by Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:70-77 [Journal]
  10. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
    Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:78-95 [Journal]
  11. Domenico Zito, Domenico Pepe, Bruno Neri
    RFID Systems: Passive versus Active and a Novel Low-Power RF Transceiver for IEEE 802.15.4 (ZigBee) Standard Based Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:96-105 [Journal]
  12. Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy
    Low-Power Hierarchical Scan Test for Multiple Clock Domains. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:106-118 [Journal]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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