Journals in DBLP

VLSI Signal Processing
2006, volume: 42, number: 3

1. Yongru Gu, Keshab K. Parhi
   Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:211-221 [Journal]
   
2. Paul Salama, Maher E. Rizkalla, Michael Eckbauer
   VHDL Implementation of the Fast Wavelet Transform. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:223-239 [Journal]
   
3. Shao-Yi Chien, Bing-Yu Hsieh, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen
   Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:241-255 [Journal]
   
4. Kent E. Wires, Michael J. Schulte
   Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:257-272 [Journal]
   
5. Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés
   A Novel FPGA Architecture of a 2-D Wavelet Transform. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:273-284 [Journal]
   
6. José Luis Imaña, Juan Manuel Sánchez
   Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2^m) Generated by AOPs. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:285-296 [Journal]
   
7. Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen
   Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:297-320 [Journal]
   
8. Tinku Acharya, Chaitali Chakrabarti
   A Survey on Lifting-based Discrete Wavelet Transform Architectures. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:42, n:3, pp:321-339 [Journal]