Journals in DBLP

VLSI Signal Processing
2006, volume: 43, number: 2-3

1. Andy D. Pimentel, Stamatis Vassiliadis
   Editorial. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:111- [Journal]
   
2. Jarmo Takala, Konsta Punkka
   Scalable FFT Processors and Pipelined Butterfly Units. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:113-123 [Journal]
   
3. Michael Hosemann, Gerhard Fettweis
   On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:125-142 [Journal]
   
4. Michael Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis
   A Low-Power Multithreaded Processor for Software Defined Radio. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:143-159 [Journal]
   
5. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
   Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:161-172 [Journal]
   
6. Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
   Requirements for Interfacing IP-Components in Re-configurable Platforms. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:173-184 [Journal]
   
7. Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna
   HIBI Communication Network for System-on-Chip. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:185-205 [Journal]
   
8. John McAllister, Roger Woods, Richard Walke, D. Reilly
   Multidimensional DSP Core Synthesis for FPGA. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:207-221 [Journal]
   
9. Holger Blume, Thorsten von Sydow, Tobias G. Noll
   A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain. [Citation Graph (0, 0)][DBLP]
   VLSI Signal Processing, 2006, v:43, n:2-3, pp:223-233 [Journal]
   
10. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:235-246 [Journal]
    
11. Jürgen Teich, Shuvra S. Bhattacharyya
    Analysis of Dataflow Programs with Interval-limited Data-rates. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:247-258 [Journal]