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Journals in DBLP

VLSI Signal Processing
2006, volume: 44, number: 3

  1. Yuanbin Guo, Joseph R. Cavallaro
    A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:195-217 [Journal]
  2. Zhan Guo, Peter Nilsson
    A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:219-230 [Journal]
  3. Junhyung Um, Taewhan Kim
    Resource Sharing Combined with Layout Effects in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:231-243 [Journal]
  4. Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
    Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:245-267 [Journal]
  5. Young-Jun Kim, Taewhan Kim
    A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:269-283 [Journal]
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