Journals in DBLP

J. Electronic Testing
2005, volume: 21, number: 3

1. Vishwani D. Agrawal
   Editorial. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:199- [Journal]
   
2. Bruce C. Kim
   Test Technology Technical Council Newsletter. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:201- [Journal]
   
3. Adoración Rueda, Michel Renovell, José Luis Huertas
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:203- [Journal]
   
4. Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
   An On-Chip Spectrum Analyzer for Analog Built-In Testing. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:205-219 [Journal]
   
5. Diego Vázquez, Gloria Huertas, África Luque, Manuel J. Barragan Asian, Gildas Leger, Adoración Rueda, José Luis Huertas
   Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:221-232 [Journal]
   
6. Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues
   On-Chip Pseudorandom MEMS Testing. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:233-241 [Journal]
   
7. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
   Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:243-255 [Journal]
   
8. R. Sanahuja, V. Barcons, L. Balado, Joan Figueras
   Testing Biquad Filters under Parametric Shifts Using X-Y Zoning. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:257-265 [Journal]
   
9. Martin John Burbidge
   Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:3, pp:267-281 [Journal]
   
10. Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento
    Low Cost BIST for Static and Dynamic Testing of ADCs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:283-290 [Journal]
    
11. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:291-298 [Journal]
    
12. Carsten Wegener, Michael Peter Kennedy
    Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:299-310 [Journal]
    
13. José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
    Multi-VDD Testing for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:311-322 [Journal]
    
14. Soumendu Bhattacharya, Achintya Halder, Ganesh Srinivasan, Abhijit Chatterjee
    Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:323-339 [Journal]